Machine-written summary
Summary written by Claude Haiku from the source advisory. Not reviewed by a person.
Packages risc0-zkvm 2.0.0 through 2.0.2 and risc0-circuit-rv32im 2.0.0 through 2.0.3 are affected by a missing constraint in the rv32im circuit that lets a malicious prover make the RISC-V virtual machine treat the rs1 register as equal to rs2 in 3-register instructions such as remu and divu. Users of risc0-zkvm should upgrade to version 2.1.0, and users of risc0-circuit-rv32im should upgrade to version 2.0.4. Smart contract users of the official RISC Zero Verifier Router need no action, as version 2.0 has been disabled there.
Not analysed yet
We haven’t published our analysis of this Advisory yet. Once a person has reviewed it, this page will say what’s vulnerable, what has to be true for your app to be affected, and how to check.
Severity and exploitation
| Score | Rating | CVSS | Vector | Source |
|---|---|---|---|---|
| 2.7 | Low | 4.0 | CVSS:4.0/AV:N/AC:L/AT:N/PR:N/UI:N/VC:N/VI:L/VA:N/SC:N/SI:N/SA:N/E:U | CNA (GitHub_M) |
- CISA KEV Not listed.
- EPSS 0.0027, the 19th percentile, on 11 Nov 2026: FIRST’s estimate of the chance of exploitation in the next 30 days.
Timeline
- 31 Oct 2026, 15:19 UTC First seen by agentprime
- 31 Oct 2026, 15:19 UTC Confirmed by OSV
Sources
- GitHub Advisory Database: GHSA-g3qg-6746-3mg9
- OSV: GHSA-g3qg-6746-3mg9
- github.com/risc0/risc0/security/advisories/GHSA-g3qg-6746-3mg9
- nvd.nist.gov/vuln/detail/CVE-2025-52484
- github.com/risc0/risc0/pull/3181
- github.com/risc0/zirgen/pull/238
- github.com/risc0/risc0/commit/006d86c363b16d2b2ac42d32d832a209ff8ab4c9
- github.com/risc0/risc0/commit/1873bbb8a56793edd1f6195242d184cf6cc5175d
- github.com/risc0/risc0/commit/67f2d81c638bff5f4fcfe11a084ebb34799b7a89
- github.com/risc0/zirgen/commit/e0e2918302c93e956f73ca2e44aef2b861d8c3ae
- github.com/risc0/risc0